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Extensive Summary of Agreements by Topic

Multi-Cell PUSCH/PDSCH Scheduling with a Single DCI

1. Scheduling Parameters:
• Common FDRA and MCS are applied to PUSCHs/PDSCHs on a cell as in Rel-16/17 multi-PUSCH/PDSCH scheduling.
• HARQ process number is incremented for subsequent PUSCHs/PDSCHs on the cell.
2. NDI Field Options in DCI Format 0_3/1_3:
• Option 1: Number of bits equals the maximum number of schedulable PUSCHs/PDSCHs on the cell.
• Option 2: Number of bits equals the actual number of scheduled PUSCHs/PDSCHs on the cell.
• Option 3: One bit NDI for a single scheduled PUSCH/PDSCH; otherwise, Option 1 applies.
3. RV Field Options in DCI Format 0_3/1_3:
• Option 1: Number of bits based on maximum schedulable PUSCHs/PDSCHs and RV configuration.
• Option 2: Number of bits based on actual scheduled PUSCHs/PDSCHs and RV configuration.
• Option 3: One bit RV for a single scheduled PUSCH/PDSCH; otherwise, Option 1 applies.
4. TDRA Field in DCI Format 0_3/1_3:
• Indicates one row from a joint TDRA table, with each row containing one TDRA index for each BWP of each cell.
5. HARQ-ACK Bundling:
• Time-domain HARQ-ACK bundling is supported.
6. Scheduling Scenarios:
• Support for scheduling up to two different SCS types and various combinations of FR1 and FR2 cells.
7. Payload Size Limitation:
• Maximum number of PUSCHs/PDSCHs for a scheduled cell by DCI format 0_3/1_3 is 8.
• Payload size exceeding 140 bits is not supported in Rel-19.
8. HARQ-ACK Codebook:
• Type-2 HARQ-ACK codebook is generated by concatenating two sub-codebooks:
• First sub-codebook for single PDSCH scheduling or single cell scheduling with nrofHARQ-BundlingGroups = 1.
• Second sub-codebook for multi-cell scheduling or single cell scheduling with nrofHARQ-BundlingGroups > 1.
9. HARQ-ACK Information Bits:
• For the second sub-codebook, the number of HARQ-ACK information bits is determined by RRC configuration or explicitly configured.
10. UL-SCH Field:
• 1 bit UL-SCH field is always present in DCI format 0_3.
11. NDI/RV Indication Placement:
• NDI and RV bits are placed in LSBs based on SLIV position in the TDRA row, with padding bits in MSBs.

Low Band Carrier Aggregation via Switching

1. Semi-Static Configuration:
• Support semi-static switching patterns based on UE-specific RRC configuration between:
• Case 1: Tx/Rx on FDD carrier 1 and no Rx on SDL carrier 2.
• Case 2: Rx on SDL carrier 2 and no Tx/Rx on FDD carrier 1.
2. Carrier and SCS Details:
• FDD carrier 1 is PCell, SDL carrier 2 is SCell.
• SCS is 15 kHz on both carriers.
3. Switching Pattern Restrictions:
• Same slot cannot contain symbols configured for both FDD and SDL carriers.
• Switching pattern and gap are based on PCell downlink timing.
4. Bitmap Design for Switching Pattern:
• NW configures periodicity and bitmap of P bits, where:
• ‘0’ indicates FDD carrier 1.
• ‘1’ indicates SDL carrier 2.
• Restriction on maximum X switches within Y slots.
5. Switching Gap Location:
• For SDL to FDD switch, gap is at SDL carrier.
• For FDD to SDL switch, options include:
• Alt 1: Gap at FDD carrier.
• Alt 2: NW configures gap location.
• Alt 3: Gap at SDL carrier.
6. Switching Gap Duration:
• RRC-configured duration, different for FDD to SDL and SDL to FDD switches.
• NW ensures gap covers switching period and UL TA (if needed).
7. Periodic Switching Pattern:
• Semi-static switching pattern is periodic with a periodicity of 40 ms.

General Agreements

1. Higher Layer Signaling:
• Rapporteur to provide initial input on higher layer signaling under agenda item 9.12.
2. Future Discussions:
• Placeholder for low band carrier aggregation discussions starting in 2025.Q2.

This summary consolidates the agreements across sessions and topics, providing a comprehensive overview of the decisions made.